This invention relates to testing integrated circuits, and more particularly, to at-speed logic testing using scan chain circuitry.
Integrated circuits typically contain numerous circuit components such as metal-oxide-semiconductor transistors. These components may be used to form a variety of combinational and sequential logic circuits. A modern integrated circuit may contain thousands or millions of circuit components.
Particularly in integrated circuits such as these, testing is challenging. The number of input-output pins on an integrated circuit is limited. This can make it difficult to determine whether circuitry that is located within the interior of the integrated circuit is functioning properly.
To facilitate testing of integrated circuits, many integrated circuits are provided with scan chain circuitry. Scan chain circuitry may be selectively formed from chains of linked registers. These chains may be provided throughout an integrated circuit. During normal operation, the scan chain circuitry can be disabled. During testing, the scan chains can be used to load test data and to unload captured test results.
For example, when it is desired to apply a particular set of test inputs to circuitry within an integrated circuit under test, test data can be loaded into the integrated circuit through a scan chain. After the test data has been loaded, one or more clock cycles may be applied to the circuitry to test the operation of the circuitry. The results of this type of test may be captured and unloaded from the integrated circuit using scan chain circuitry. Analysis of the captured test results may help reveal whether the circuitry is responding properly to the input data. For example, the presence of a fault may be revealed if a logic one was captured when a logic zero was expected.
Circuit faults that are sensitive to timing are not always detected when performing conventional scan tests. Accordingly, so-called transition delay fault (TDF) testing is performed at speed. If, for example, an integrated circuit is designed to operate with a clock speed of 400 MHz, TDF testing may be performed that subjects circuitry under test to a 400 MHz clock.
To ensure satisfactory test coverage, TDF testing may be performed using scan chains. Conventional scan chain TDF testing involves the use of launch-off-capture (LOC) and launch-off-shift (LOS) methodologies.
Conventional launch-off-capture techniques rely partly on the operation of user logic. User logic that is normally used in implementing logic functions for an end user of the integrated circuit being tested is used in generating a launch pulse. The launch pulse is then used in performing an at-speed test. Although this technique may often be satisfactory, it may be difficult or impossible to produce the desired launch pulse from user logic in some integrated circuits, leading to incomplete test coverage.
Conventional launch-off-shift techniques can often provide better test coverage than launch-off-capture techniques. With launch-off-shift arrangements, a high speed scan enable signal is applied to appropriate registers in a scan chain. The high speed scan enable signal facilitates generation of the launch pulse and avoids reliance on user logic in generating the launch pulse. While this type of approach may often be satisfactory, precise control of the scan enable and clock signals is required. Adequately addressing these timing issues can require the use of costly high speed test equipment or complex on-chip test circuitry.
Programmable logic device integrated circuits are a type of integrated circuit in which a user can configure logic to perform a desired custom logic function. Programmable logic circuits often contain logic elements that include scan cells for forming scan chains.
It would be desirable to be able to provide improved scan chain circuitry for performing at speed scan chain logic tests for integrated circuits such as such as programmable logic device integrated circuits.